1hz: Clock Divider Verilog 50 Mhz

reg [$clog2(MAX_COUNT+1)-1:0] counter;

// Stage 2: 100 Hz → 10 Hz (divide by 10) clock_divider #(100, 10) stage2 (clk_100hz, rst_n, clk_10hz); clock divider verilog 50 mhz 1hz

localparam COUNTER_MAX = 25_000_000 - 1; // 24,999,999 reg [24:0] counter; // 25 bits needed (2^25 = 33,554,432 > 25M) reg [$clog2(MAX_COUNT+1)-1:0] counter; // Stage 2: 100 Hz

// Generate 50 MHz clock (period = 20 ns) initial begin clk_50mhz = 0; forever #10 clk_50mhz = ~clk_50mhz; // 10ns half period = 20ns full period end reg [$clog2(MAX_COUNT+1)-1:0] counter

always @(posedge clk_50mhz or negedge rst_n) begin if (!rst_n) begin counter <= 0; clk_1hz <= 0; end else begin if (counter == COUNTER_MAX) begin counter <= 0; clk_1hz <= ~clk_1hz; // Toggle output end else begin counter <= counter + 1; end end end endmodule module clock_divider_50M_to_1Hz_v2 ( input wire clk_50mhz, input wire rst_n, output reg clk_1hz ); // Division factor: 50,000,000 / 2 = 25,000,000 counts per half cycle localparam HALF_CYCLE = 25_000_000 - 1; reg [24:0] count;

// Stage 1: 50 MHz → 100 Hz (divide by 500,000) clock_divider #(50_000_000, 100) stage1 (clk_50mhz, rst_n, clk_100hz);

always @(posedge clk_in or negedge rst_n) begin if (!rst_n) begin counter <= 0; clk_out <= 0; end else begin if (counter == MAX_COUNT) begin counter <= 0; clk_out <= ~clk_out; end else begin counter <= counter + 1; end end end endmodule `timescale 1ns / 1ps module tb_clock_divider;